Computers and computer components communicate using either serial or parallel data transmission. Parallel data transmission consists of sending several bits simultaneously, over separate channels, while serial data transmission consists of sending data bits one at a time over a single channel. While parallel transmission allows for high speed transmission between components that are in close proximity to each other, it is often not conducive to data transmission over longer distances. Serial transmission offers several advantages for transmission over longer distances (e.g., lower cost as only one channel is required). One technique used to capture the advantages of both data transmission methods is to convert parallel data to serial data for transmission over a channel and then convert the serial data back to parallel data. In order to accomplish this without unduly limiting the transfer rate, a channel with sufficient bandwidth may be used for the data transmission.
In response to this need for higher bandwidth data communication architectures, data communication architechures such as the SERDES (serial/deserializer) architecture were developed. SERDES is a protocol to encode and decode data according to a predefined scheme (e.g., eight-bit/ten-bit encoding). The encoded data is communicated over one or more communication channels from the serializer to a corresponding deserializer for decoding. Using the SERDES architecture, the bandwidth of data communications between cooperating computer components is increased.
Crossbar switches are often used to provide switching in high bandwidth data communication architectures such as SERDES. Crossbar switches are used to interconnect devices that are in communication within a computer system. The basic function of a crossbar switch is to receive data from one device and route it to another device. The crossbar switches are commonly formed on application specific integrated circuits (ASICs). The ASICs are generally packaged on a chip (e.g., silicon) having a plurality of pins through which connection is made to the elements on the chip.
It is common practice to test the ASICs to verify proper functionality of the crossbar switch. Various testing techniques have been employed to test ASICs at the chip level. These testing techniques typically involve the use of a dedicated debug port formed on the ASIC. Typically, the functionality of the various elements contained on the ASIC is monitored by connecting the output of the dedicated debug port to a monitoring device, such as a logic analyzer. However, this technique has several drawbacks. Because an additional port is required to act as the dedicated debug port, space on the chip is consumed. Additionally, input/output pins are required to be dedicated to the dedicated debug port. After verifying the functionality of the ASIC, the debug port and associated input/output pins are normally not used again, making the debug port an inefficient use of chip resources.